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43- 46 The one-transistor, T-cell, flash memory array has evolved from the conventional T-cell EPROM technology The top view and cross section through the transistor parallel to the word line are the same as that shown in Figure 814 The gate oxide is thinned to ,- 10 nm to allow the cells to be erased by FN tunneling from the floating gate to the substrate or the source For some erase schemes, the source diffusion is modified as discussed in the following paragraphs The cells are programmed the same way as the T-cell EPROM is programmed Because the flash memories are usually intended for applications involving insystem programming, it is common for the memories to have circuitry to implement algorithms for efficient programming and threshold margin measurement designed into the memory chips rather than relying on intelligence in a programming system as is the usual case for EPROMs.

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The read operation and design considerations for T-cell flash memory arrays also mirror those for T-cell EPROM memory arrays Erase can be accomplished by causing electrons to tunnel either to the source or to a p well 47 Tunneling to the source is very nonuniform, while tunneling to a p well provides uniform erase There are advantages and disadvantages to both approaches Tunneling to the source involves biasing the source to a high positive potential with respect to the floating gate so that a high field is established across the gate oxide separating the junction from the floating gate This causes a high field in the silicon in the vicinity of the junction as illustrated in Figure 89 If the junction is abrupt, there is a real possibility that the high field in the silicon will lead to gateaided breakdown.

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Table 10.15 Semaphore Settings PARAMETER semmap semmni semmns semmnu semmsl semopm semume semusz semvmx semaem DESCRIPTION Number of entries on the semaphore map should be smaller than semi. Maximum number of systemwide semaphore sets. Maximum number of semaphores in the system (should be set to equal semmni times semsl). Maximum number of undo structures in the system should be set to same value as semmni. Maximum number of semaphores per semaphore set. Maximum number of semaphore operations that can be performed in each semop call. Maximum number of undo structures per process. Number of bytes required for semume undo structures. Maximum value of a semaphore. Maximum adjust-on-exit value.

The resulting currents would be too large for the intended mass operation To avoid gate-aided breakdown, common practice is to provide a graded source junction, as illustrated in Figure 826a Nonuniform erase can be accomplished by either applying a bias of - 12 V to the source with the control gate grounded or by applying - 5 V to the source with the control gate biased at about - 10 V48 The drain is allowed to float in either case The advantage of the negative gate erase is that the source current is supplied from a low voltage supply, often directly from VDD The significance of this is that the source current during erase can be as large as 1 nA/cell Although 1 nA may seem like a small current, when cumulated over 1 M cells, the current is -1 mA.

Summary

where rj is as defined in Figure 3.14. For narrow width MOSFETs, the effective depletion width is greater than the physical gate width because of the spreading of the depletion region beyond the physical gate width. The effective gate width can be expressed as

Generating 1 mA from an on-chip charge pump is difficult; consequently, negative gate erase is.

(4.A.18) (4.A.19)

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